1. Field of the Invention
The invention relates to a semiconductor wafer with improved local flatness (nanotopology), and to a process for producing a semiconductor wafer of this type.
2. The Prior Art
The electronics, microelectronics and microelectromechanics industries are substantially based on the mechanical and chemical shaping, machining and structuring of silicon and a few other semiconductor materials, such as germanium or gallium arsenide to an increasingly fine, complex and reproducible extent. The driving force behind this technology is in particular silicon microelectronics, which, as component integration densities become ever higher, is starting to require structures which are chemically and structurally well defined on a virtually atomic scale. Particularly demanding components, for example microprocessors, typically comprise multilayer-structured component levels which are wired to one another and are separated from one another by insulating interlayers. By now, the central step in the production of multilayer components of this type is virtually exclusively chemical mechanical polishing (CMP), which is used to planarize the interlayers. A high flatness of these interlayers is a condition for the most photolithographic structuring of the next component level. Due to the lateral structure resolution required, which is currently 0.18 μm or 0.13 μm, and exposure wavelengths of below 200 nm, lithography has an extremely low exposure focus depth and therefore only functions on extremely flat exposure surfaces. To ensure that the CMP process does not break through the insulating layer and attack the components below it or thin structures which have been created so that their dimensions become uneven, even the starting surface, i.e. the surface of the silicon substrate base, has to be as perfectly flat as possible.
Until a few years ago, the flatness values required for the substrate wafers were only globally defined and specified for the overall wafer or for the surface area taken up by individual components. For example, the characteristic variable TTV (total thickness variation) indicates the deviation in the wafer thickness over the entire area of the wafer. On the other hand, the characteristic variable SFQR (site focal-plane least-square deviation range (peak to valley)) relates to the extent of individual component assemblies (sites; exposure points; e.g. a microprocessor with an area of, for example, 25 mm×25 mm). In addition to these long-range characteristic variables, there have also been, and still are, stipulations for the short-range (atomic) roughness on the length scale of the individual components, since the residual roughness of the starting surface directly affects the functioning of the individual components which are structured on this starting surface and formed therefrom. With the advent of the CMP process for planarizing of the component interlayers in multilayer components on a large scale, in addition to these traditional, in particular short-range and long-range stipulation areas, maximum residual unevennesses in the millimeter range and slightly above are now also specified. Structures within this scope are referred to as nanotopology.
The term “nanotopology” or “nanotopography” is defined more accurately by SEMI (Semiconductor Equipment and Materials International) as the deviation in planarity of the entire wafer front surface in the region of three-dimensional wavelengths of approximately 0.2 to 20 mm (lateral correlation length) and within the “quality zone” (FQA, “fixed quality area”; surface region for which the wafer properties demanded in the product specification have to be satisfied).
In particular, therefore, features of a wafer which are classified as belonging to the nanotopology differ from other features with variations in height of a comparable order of magnitude by virtue of their characteristic lateral extent (correlation lengths or location frequencies). For example, even nanotopology features with a height (peak to valley) of only 20 nm lead to a change in the thicknesses of film structures which are applied to the semiconductor wafers, having an adverse effect on functioning of the components and appearing during fabrication as uneven coloring (discoloration) of the film.
Good nanotopology is particularly important for a successful CMP process which is used, for example, to level layers of this type. The rigidity of the polishing cloths which are used during the CMP, as well as other process parameters of the CMP, result in preferred smoothing precisely in the nanotopology range. This results in inhomogeneous thinning of component structures on a semiconductor wafer, which is associated with poor nanotopology in the CMP process. Consequently, the component characteristic deteriorates, possibly to the extent of a short circuit occurring when the interlayers (dielectrics) are broken through.
The nanotopology is measured by scanning the entire wafer surface, with different sizes of measurement fields, completely and with an overlap. Not one of the variations in the height of the surface (peak to valley) found in each of these measurement fields may exceed the required maximum for the entire wafer. The measurement-field sizes are dependent on specification and are described, for example, as 2 mm×2 mm, 5 mm×5 mm and 10 mm×10 mm. For these measurement fields, for example in the case of a 0.13 μm minimum lateral feature size of the components, maximum height deviations of <20 nm, <30 nm and <50 nm are permitted. Particularly strict demands on the nanotopology apply for demanding very large scale integrated microelectronic components, which are fabricated almost exclusively using the CMP process. Because of the peculiarities of the CMP process, these demands are significantly stricter than the overall, site-referenced and microscopic residual unevenness values, and cannot be achieved, or can only be achieved with an uneconomic yield, with conventional machining sequences for production of the semiconductor wafers.
There is therefore a need to provide a semiconductor wafer whose nanotopology is so good that it satisfies the demands imposed on the starting flatness imposed by the production of particularly demanding microelectronic components, in particular in multilayer technology and with a CMP step, for a 0.13 μm lateral component feature size and below and for wafer diameters of 200 mm and above.
According to the prior art, semiconductor wafers, in particular silicon wafers, are produced, starting from a low-defect monolithic single crystal by a machining sequence which comprises a number of process groups:
a) separating (“sawing”) the single crystal into wafers,
b) mechanical machining,
c) chemical machining, and
d) chemical-mechanical machining.
In addition, a wide range of further steps, such as cleaning, classifying, measuring and packaging steps may be carried out, but these have no influence on the flatness of the wafer surface and are therefore not considered in more detail in the text which follows.
According to the prior art, the separation a) is generally carried out by means of an internal-diameter saw (ID), a wire saw (multi-wire saw, MWS), by separation/planarization grinding (grind-slicing, GS), by means of a band saw (single cut) or a web saw (multiple cut).
The mechanical machining b) comprises the rounding of the wafer edge and the planarization of the wafer surface by means of mechanically abrasive, material-removing steps. The edge rounding (edge/notch rounding, ENR) is carried out by grinding or polishing using round, strip-like or similar tools. The planarization of the wafer surface takes place in a batch, i.e. for a plurality of wafers simultaneously, by lapping with unbonded grain using a lapping slurry, or as a single-wafer process by grinding with bonded grain. In the case of grinding, one side of the semiconductor wafer is fixed to a chuck by vacuum and the other side is machined by a grinding disk which is covered with abrasive grain. The machining of the two sides of the semiconductor wafer takes place sequentially. In general, batch double-side grinding processes with lapping kinematics are used, in which bonded abrasive or abrasive which has been applied to coverings (cloth), where it has “nested” in a quasi-fixed state, is located on two large, opposite working disks, between which the semiconductor wafers are ground in a semi-free state, so that they can move on both sides in guide cages, in the same way as during lapping. There is also the process known as “flat honing”, in which the working disks are fitted with pellets covered with hard material.
The chemical machining c) comprises one or more cleaning and etching steps. During etching—in batches or for each single wafer—material is removed from both sides, with the object of “deep cleaning”, removing the surface zones with damaged crystallinity and reducing the mechanical surface stresses after the mechanical machining. Numerous linear sequences are known which eliminate the etching, since the amount of material removed by etching represents additional consumption of material and increases the overall machining outlay involved in semiconductor wafer manufacture, and moreover is generally associated with a deterioration in the wafer geometry (flatness, dimensional accuracy) which has previously been achieved during the mechanical machining.
The chemical-mechanical machining d) comprises a plurality of polishing steps. According to the prior art, these steps include an optional multistage prepolishing process and a general multistage fine-polishing process. Prepolishing (stock-removal polishing, primary polishing) and fine polishing (haze-free polishing, secondary polishing) may in this case be carried out in the form of a plurality of workpiece clamps on different machines with intervening cleaning, classifying, measuring and other steps, or in integrated machine tools in which the semiconductor wafers are transferred directly to the various polishing plates with different polishing cloths whose properties are in each case optimized for prepolishing and fine polishing.
The polishing step is generally a chemical-mechanical polishing step in which colloidal-disperse, chemically modified silica sol (slurry) removes material partly by mechanical abrasion but predominantly by chemical attack, as a result of a relative movement between the semiconductor wafers and a polishing cloth, this removal of material finishing the planarization of the wafers so that there are few if any crystal defects (geometry) and microscopically smoothing the surface (roughness).
Single-side polishing processes are used for prepolishing and fine polishing, and double-side polishing processes are also used for the prepolishing. In the case of single-side polishing, the semiconductor wafers are bonded on their back surface to a support plate (cement polishing), and are held by a vacuum or adhere by friction to what is known as a rear backing pad (primarily in the case of fine polishing). There are both individual-wafer and batch polishing processes for single-side polishing. The fine polishing is only applied to what will subsequently be the front surface of the semiconductor wafer. Depending on the desired finish of what will subsequently be the wafer back surface, only the front surface is processed during the prepolishing, and consequently the back surface retains the roughness which has been predetermined by the previous processes, or alternatively both sides are processed by sequential single-side polishing or by simultaneous double-side polishing. Double-side polishing is only used for the prepolishing process. The prior art also includes a batch process in which the semiconductor wafers are inserted into thin guide cages in such a manner that they can move semi-freely and are simultaneously polished on both sides between two plates with polishing cloths using lapping kinematics.
Furthermore, the edge of the wafer is generally finish-machined (polished) before the prepolishing. However, other sequences are also known, including those which provide for integrated prerounding (chamfering) and fine-rounding (edge polishing) in a single step.
It is known that a particularly good geometry of the machined wafers can be achieved by using a simultaneous double-side grinding process (double disk grinding, DDG) during the mechanical machining b). However, a common feature of all the machining sequences which have previously been disclosed and include a simultaneous double-side grinding step is that they involve a plurality of mechanical (material-removing) machining steps.
Until now, in principle only machining sequences with a DDG step in which DDG is used either only as a rough preliminary grinding step or in a two-stage process as preliminary grinding and finish-grinding step, have been considered possible and achievable. EP 1 049 145 A1 has disclosed a machining sequence which involves a DDG preliminary grinding step (roughing), followed by one or more (sequential) single-side finish-grinding steps (finishing). By contrast, U.S. Pat. No. 6,066,565 describes the use of the DDG process in a two-stage process with double-side preliminary grinding and double-side finish-grinding. This requires two machines and requires the workpiece to be clamped a number of times.
With the abovementioned machining sequences, the general advantages of DDG machining are obtained at the expense of the drawbacks of mechanical machining in a plurality of steps which has always been considered necessary when using DDG. The multistage partial mechanical machining sequences according to the prior art, which involve one or more DDG steps, have the following considerable drawbacks for the overall machining sequences based thereon:
The consumption of material increases with the number of machining steps. In the case of double-stage or multistage machining, overall more material is removed from the workpiece than when using single-step machining, since grinding-in and grinding-out processes and also the “warm-up grinding” until the thermal equilibrium is established occur a number of times. Moreover, material-removal additions which allow the minimum removal of material which is required for the quality objectives of each individual step to be achieved reliably even with fluctuating initial qualities of the workpieces, have to be applied to the use of material a number of times.
In addition to the amount of material removed, the scrap rate also increases with the number of machining steps, since the yield of each individual step is below 100%.
In addition, long process sequences with a large number of machining steps are distinguished by a low flexibility, poor availability of the overall machining sequence and high throughput times. In general, the overall availability of the machining sequence falls as the number of individual steps increases. To avoid production waste, therefore, it is necessary to keep buffer stores and spare machines.
Overall, therefore, the production costs of semiconductor wafers rise with the number of machining steps. This even applies to the multistage mechanical machining sequences according to the prior art, which include an otherwise advantageous DDG step.